A. Field of the Invention
The present invention relates to a semiconductor device and a method for producing a semiconductor device, and more particularly, to a semiconductor device, such as a diode or an insulated gate bipolar transistor (IGBT) including an n-type field stop layer, and a method for producing a semiconductor device.
B. Description of the Related Art
As a semiconductor device used in a power semiconductor device, for example, there is a diode or an IGBT with a breakdown voltage of 400 V, 600 V, 1200 V, 1700 V, 3300 V, or a higher one. The diode or the IGBT is used in a power conversion apparatus such as a converter or an inverter. The power semiconductor device requires good electrical characteristics, such as low loss, high efficiency, and a high breakdown voltage, and low costs. For example, a semiconductor device has been known in which a donor layer which will be an n-type field stop (FS) layer is provided in an n− drift layer to improve switching characteristics. The semiconductor device including the n-type FS layer according to the related art will be described using a diode as an example.
FIG. 6 is a cross-sectional view illustrating a main portion of the diode including the n-type field stop layer according to the related art. In diode 100a shown in FIG. 6, p-type anode region 2 is formed in a first main surface (front surface 1b) of n− semiconductor substrate 1 which will be an n− drift layer that is so thin that a predetermined breakdown voltage is obtained. N+ cathode layer 3 is formed in a second main surface (rear surface 1a) of n− semiconductor substrate 1. Then, a plurality of p-type layers and a metal electrode coming into contact with the p-type layers which form junction edge termination structure 4 are formed in the outer circumference of p-type anode region 2 on the front surface 1b of n+ semiconductor substrate 1 so as to surround p-type anode region 2.
Reference numeral 5 denotes an anode electrode, reference numeral 6 denotes a cathode electrode, reference numeral 8 denotes an insulating film, and reference numeral 9a denotes an n-type FS layer. A donor layer denoted by reference numeral 18a forms n-type FS layer 9a. N-type FS layer 9a is an n-type diffusion layer which has an impurity concentration higher than n− drift layer 1, has a high impurity concentration peak at a relatively deep position (for example, at a depth of 3 μm to several tens of micrometers) in the n− drift layer from rear surface 1a of n− semiconductor substrate 1, and has a large width (a large thickness) in the depth direction of the substrate.
In the diode or the IGBT having the above-mentioned structure, in order to improve the switching characteristics, a method has been known which generates crystal defects in the n− drift layer using electron beam irradiation and controls a carrier lifetime. In addition, in the diode or the IGBT, in order to reduce switching loss, it is necessary to control carrier concentration at a deep position from the front surface 1b to rear surface 1a of n− semiconductor substrate 1.
As a method of controlling the carrier concentration in n− semiconductor substrate 1 which will be an n− drift layer, a method has been known which performs proton implantation capable of forming a deep range in n− semiconductor substrate 1 from rear surface 1a of n− semiconductor substrate 1 at a relatively low acceleration voltage and generates donor layer 18a in an n− silicon substrate, which is n− semiconductor substrate 1, as shown in FIG. 6. This method performs proton implantation for a region including oxygen to form n-type FS layer 9a which is donor layer 18a including the crystal defects formed by the proton implantation.
FIG. 7 is a characteristic diagram illustrating a carrier concentration distribution on the line X1-X2 of FIG. 6. FIG. 7 illustrates the carrier concentration distribution of donor layer 18a which is formed in n− semiconductor substrate 1 by the proton implantation. As shown in FIG. 7, donor layer 18a formed by the proton implantation has an impurity concentration distribution in which impurity concentration has a peak position at a predetermined depth from rear surface 1a of n− semiconductor substrate 1 and is reduced from the peak position to p-type anode region 2 and n+ cathode layer 3. In FIG. 7, the vertical axis is carrier concentration B and the horizontal axis is a depth C from the interface between n+ cathode layer 3 and donor layer 18a (n-type FS layer 9a).
The proton implantation is used to control a lifetime killer, in addition to the generation of donors. A method has been known in which crystal defects serving as the lifetime killers are generated in the semiconductor substrate using the proton implantation. The generation of the crystal defects in the semiconductor substrate by the proton implantation makes it possible to control the carrier lifetime of the diode or the IGBT, but has an adverse effect on electrical characteristics. For example, the breakdown voltage is reduced or the leakage current is increased by the crystal defects. Therefore, it is possible to control the amount of crystal defects for generating donors and the amount of crystal defects which will be the lifetime killers at the same time.
The following Patent Literature 1 discloses heat treatment conditions required to obtain the desired element characteristics in a method of generating donors using proton implantation. The following Patent Literature 2 discloses oxygen concentration required to increase the donor generation rate in the generation of donors by proton implantation.
Patent Literature 1: United States patent application, Publication No. 2006/0286753
Patent Literature 2: Pamphlet of PCT International Publication No. 2007/55352